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74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
October 1995 Revised April 1999
74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
General Description
The LCX841 consists of ten latches with 3-STATE outputs for bus organized system applications. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX841 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs s 2.3V - 3.6V VCC specifications provided s 8.0 ns tPD max (VCC = 3.3V), 10 A ICC max s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s 24 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human Body Model > 2000V Machine Model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74LCX841WM 74LCX841MSA 74LCX841MTC Package Number M24B MSA24 MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
(c) 1999 Fairchild Semiconductor Corporation
DS012575.prf
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74LCX841
Pin Descriptions
Pin Names D0-D9 LE OE O0-O9 Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs
Truth Table
Inputs OE X H H H L L L LE X H H L H H L D X L H X L H X Internal Q X L H NC L H NC Output O Z Z Z Z L H NC High Z High Z High Z Latched Transparent Transparent Latched Function
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impendance NC = No Change
Functional Description
The LCX841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LCX841
Absolute Maximum Ratings(Note 2)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 -50 -50 +50 50 100 100 -65 to +150 (Note 4) Min Operating Data Retention VI VO IOH/IOL Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC = 3.0V - 3.6V VCC = 2.7V - 3.0V VCC = 2.3V - 2.7V TA t/V Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V - 2.0V, VCC = 3.0V -40 0 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 24 12 8 85 10 C ns/V mA Units V V V Output in 3-STATE Output in HIGH or LOW State (Note 3) VI < GND VO < GND VO > VCC mA mA mA C Conditions Units V V V mA mA
Recommended Operating Conditions
Symbol VCC Supply Voltage Parameter
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -8 mA IOH = -12 mA IOH = -18 mA IOH = -24 mA VOL LOW Level Output Voltage IOH = 100 A IOH = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA II IOZ IOFF Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current 0 VI 5.5V 0 VO 5.5V VI = V IH or VIL VI or VO = 5.5V 0 10 Conditions VCC (V) 2.3 - 2.7 2.7 - 3.6 2.3 - 2.7 2.7 - 3.6 2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 - 3.6 VCC - 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 5.0 5.0 A A A V V TA = -40C to +85C Min 1.7 2.0 0.7 0.8 Max V V Units
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74LCX841
DC Electrical Characteristics
Symbol ICC ICC Parameter Quiescent Supply Current Increase in ICC per Input
(Continued)
VCC (V) 2.3 - 3.6 2.3 - 3.6 2.3 - 3.6 TA = -40C to +85C Min Max 10 10 500 A A
Conditions VI = VCC or GND 3.6V VI, VO 5.5V (Note 5) VIH = VCC - 0.6V
Units
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter VCC = 3.3V 0.3V CL = 50 pF Min tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH tS tH tW Output to Output Skew (Note 6) Setup Time Dn to LE Hold Time Dn to LE LE Pulse Width 2.5 1.5 3.3 Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max 7.0 7.0 7.0 7.0 8.0 8.0 6.5 6.5 1.0 1.0 2.5 1.5 3.3 4.0 2.0 4.0 VCC = 2.7V CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max 7.5 7.5 7.5 7.5 8.5 8.5 7.0 7.0 VCC = 2.5V 0.2V CL = 30 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max 8.4 8.4 8.4 8.4 9.6 9.6 7.8 7.8 ns ns ns ns ns ns ns ns Units
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25C Typical 0.8 0.6 -0.8 -0.6 Units V V
Capacitance
Symbol CIN CO CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF
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74LCX841
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC = 3.3 0.3V VCC x 2 at VCC = 2.5 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V
trise and tfall
2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
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74LCX841
Schematic Diagram Generic for LCX Family
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74LCX841
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24
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74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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